Invited speaker: Wang Guilei
Engineer at the Leading Process R&D Center, Institute of Microelectronics, Chinese Academy of Sciences
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2015
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Wang Guilei is an engineer at the Leading-edge Process R&D Center of the Institute of Microelectronics, Chinese Academy of Sciences, and is currently pursuing a doctoral degree. During his tenure, he participated in the National Key Science and Technology Project 02, engaging in the research and development of advanced thin-film processes for integrated circuits. He has made significant contributions in areas such as silicon-germanium source/drain strain (SiGe S/D Strain) and atomic-layer-deposited tungsten metal gates (ALD W Metal Gate). He possesses extensive R&D experience spanning both 12-inch and 8-inch integrated circuit production lines. To date, he has published more than 20 research papers in international academic journals and at conferences. In addition, he has filed 23 invention patent applications, three of which have already been granted U.S. patents.
Report Title: Selective Growth of Germanium-Silicon Materials and Their Application in Integrated Circuits
Introduction to the Report: Germanium-silicon strained materials are widely used in PMOS source-drain structures of integrated circuits to enhance carrier mobility in the channel and improve device performance. This paper primarily investigates key issues related to the integration of selectively epitaxially grown germanium-silicon alloys (Si1-xGe x, where 0.3 ≤ x ≤ 0.40) doped in situ with boron at a concentration of 1 × 10^20 cm^-3 into 22-nm planar and 14/16-nm three-dimensional FinFET source-drain structures. Through detailed experimental studies, we have examined the quality of selective epitaxial growth of germanium-silicon alloys, the distribution of germanium concentration, and the impact of germanium concentration on the magnitude of strain generated. Additionally, we have systematically analyzed how the pre-baking process temperature during the selective epitaxial growth of germanium-silicon alloys affects the quality of material growth and the morphology of source-drain silicon trenches or silicon fins during device integration, identifying the optimal thermal budget temperature that minimizes damage to the trench or fin morphology. Furthermore, in this study, we have developed a gas-dynamic model for the germanium-silicon reaction, which uses actual reaction parameters to simulate and investigate the effects of varying exposed silicon pattern areas on the growth rate, morphology, and strain generation of germanium-silicon alloys. The simulation results have been validated by experimental growth tests. These findings provide a theoretical foundation for optimizing layout design when integrating germanium-silicon materials into large-scale device applications.
Wang Guilei (right)
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