Semiconductors are set to embrace the 2nm era.

Currently, there are two main approaches to driving the development of the semiconductor industry: one is shrinking device dimensions, and the other is increasing silicon wafer diameters. Since increasing silicon wafer diameters requires replacing equipment across the entire production line, the primary development path at present is shrinking device dimensions. In addition, companies are also extensively adopting mature specialty processes and third-generation semiconductor materials to enhance the performance of semiconductor products, which will open up a whole new frontier for Moore’s Law.

    TSMC and Samsung Compete in Advanced Process Technologies
It is reported that TSMC’s 3-nanometer fab has already passed the environmental assessment. According to the original schedule, the world’s first 3-nanometer fab is expected to break ground in 2020 and begin mass production as early as the end of 2022.
Moreover, since Samsung announced ahead of TSMC that its 3-nanometer process will adopt a nanosheet structure with gate-all-around FinFETs, the battle between the two companies over the 3-nanometer process is about to erupt. Other reports indicate that TSMC is still sticking with an upgraded version of the FinFET architecture and may opt for materials with higher carrier mobility instead of the gate-all-around nanosheet structure.
The two companies are each making significant strides in addressing different process and architectural challenges. The key lies in identifying the performance bottlenecks and then using the most cost-effective tools in the most appropriate ways to tackle these bottlenecks individually. Whether it’s I/O, memory interfaces, or overheating logic blocks, the system’s operating speed can only match that of its slowest component.
In fact, advanced packaging is also one of the solutions. In certain cases, every advancement in the front-end process may require a completely different architecture to match it. This could involve greater co-design of software and hardware, optimizing the entire design as a single system. If there were a consistent approach to describing these devices and connecting them together, adopting methods such as chiplets could save considerable time.
Currently, there are at least six mainstream chip/chiplet combination approaches, with many more in development. It’s easy to imagine that each chip vendor will rapidly offer customized solutions tailored to factors such as price, power consumption, performance, and even regional standards. Thus, while chips used for high-performance computing (HPC) and 5G development may require the latest 2nm process technology, their complementary components—such as 16nm SerDes, 28nm power modules, and 40nm security chips—could well be based on older processes, yet all of these components will be integrated into a single package.
    Cost is a key factor.
In the semiconductor industry, cost factors are critically important. Data shows that R&D costs for the 7nm process must be at least 300 million U.S. dollars, while the average cost for the 5nm process is 542 million U.S. dollars. The starting price for the 3nm and 2nm processes is roughly around 1 billion U.S. dollars.
According to the latest reports, TSMC’s 3nm process chips, originally scheduled for pilot production in June 2020, may now be delayed until October due to the pandemic. TSMC’s total investment in the 3nm process amounts to as much as NT$1.5 trillion—roughly US$50 billion. So far, at least US$20 billion has already been spent on construction of the new fab, underscoring just how massive the investment is.
Recently, TSMC officially unveiled the detailed specifications of its latest 3nm process. Its transistor density has reached an unprecedented 250 million transistors per square millimeter. Compared to the 5nm process, power consumption has been reduced by 25% to 30%, and performance has improved by 10% to 15%.
TSMC reiterated that each node—from 7nm to 5nm and on to the future 3nm—is a full-node performance upgrade. This differs from competitors, whose every node represents only partial performance optimization rather than a full-node performance boost. Therefore, TSMC is highly confident in its competitiveness in the future 3nm process technology.
TSMC also discussed progress in its 2nm process technology. While the company is developing 3nm technology using its sixth-generation FinFET platform, it has already begun R&D on 2nm process technology and is conducting exploratory research into technologies below 2nm.
Regarding extreme ultraviolet (EUV) technology, the goal is to reduce mask defects and process stacking errors in lithography machines, as well as to lower overall costs. TSMC stated that this year, for 2nm and more advanced processes, it will focus on improving both the quality and cost of EUV technology.
Reducing semiconductor dimensions far from being achievable simply by having EUV lithography machines. Strictly speaking, when reaching the 3nm node, even the existing FinFET architecture may no longer suffice, and a comprehensive solution will be required, taking into account factors such as device architecture, process variations, thermal effects, and the interaction between equipment and materials.
Driven by market demand for HPC and 5G technologies, the semiconductor industry’s transition to 3nm has become inevitable. TSMC and Samsung have already made commitments, though the timeline could potentially be delayed slightly. The feasibility of a 2nm process is also highly probable. However, given the exorbitant costs, numerous unresolved technical challenges, and the necessity of advanced equipment and materials, whether a 1nm process can actually be realized remains unpredictable at this stage. Nevertheless, the ultimate limit of semiconductor size reduction will inevitably be reached sooner or later.