Technical Status and Prospects of 450mm Wafer CMP Equipment

　　The typical lifecycle for upgrading wafer sizes is around 10 years. For example, the 200mm wafer was introduced in 1991, while the 300mm wafer—now widely used—was first adopted by Intel in 2001 and initially employed in 130nm-process processors. A 450mm wafer boasts more than twice the silicon area and yields significantly more chips per wafer compared to the 300mm wafer; as a result, the unit cost per chip is substantially reduced. Moreover, larger wafers enhance the efficiency of resource utilization—such as energy and water—and help mitigate the impacts of environmental pollution, the greenhouse effect, global warming, and water scarcity.

　　In 2007, ISMI (International SEMATECH Manufacture Initiative) emphasized that semiconductor manufacturing still adheres to Moore’s Law. It pointed out that in the future, production costs need to be reduced by 30%, and product development cycles need to be improved by 50%. Such demands can only be met by transitioning to a 450mm wafer size.

　　In 2008, Intel, Samsung, TSMC, ISMI, and semiconductor equipment suppliers decided to collaborate on the development of 450mm wafers. The initial goal was to establish a pilot 450mm production line by 2012. This pilot line was originally scheduled to become operational between 2013 and 2014 and to evolve into a full-scale 450mm production line by 2015–2016. This roadmap was incorporated into the ITRS (International Technology Roadmap for Semiconductors) for 2009 and 2010. However, the 2012 ITRS was revised, and all previously set targets were postponed by two years.

　　As wafer sizes continue to expand, the corresponding increase in capital investment means that semiconductor chip manufacturers must shoulder substantial upfront costs for facility construction. For instance, investing in a 100mm (4-inch) production line once cost about 100 million U.S. dollars, whereas today’s mainstream 300mm (12-inch) production lines require an investment of roughly 2 to 2.5 billion U.S. dollars. In the coming years, as we enter the 450mm era, factory automation will extend across all machine-to-machine interactions and will incorporate integrated process-monitoring systems. Moreover, increasingly sophisticated manufacturing processes will demand higher-yield wafer fabrication plants equipped with more precise process automation and advanced factory management systems. The cost of building such large-scale facilities will be at least 10 billion U.S. dollars, and could even soar to between 25 and 30 billion U.S. dollars—a level of expenditure that most companies simply cannot afford. Additionally, the upfront R&D costs are extraordinarily high. To address these challenges, the world’s five leading semiconductor companies—IBM, Intel, Samsung Electronics, TSMC, and GlobalFoundries—jointly established the Global 450 Consortium (G450C) in 2011 and set up a research and development center in Albany, New York State, U.S. To date, they have already invested 4.4 billion U.S. dollars in this initiative, accelerating the transition toward the 450mm wafer size era.

　　According to the 2012 ITRS (International Technology Roadmap for Semiconductors) plan, material and equipment manufacturers for 450mm wafer production should have established production capabilities by 2013–2014 and should provide the corresponding equipment to IDMs (Integrated Device Manufacturers) and foundries.

　　Only by enabling chip manufacturers and equipment manufacturers to achieve mutual win-win outcomes can we sustain the healthy development of the semiconductor industry. Similarly, equipment manufacturers (OEMs) need to invest a larger proportion of their R&D expenditures than before in order to meet the stringent process and technological requirements of 450mm wafers. As wafer sizes continue to increase, equipment manufacturers face ever-higher demands regarding system integration, system automation, specialized material requirements, and overall power consumption. Starting from multi-layer metal interconnects (with more than three layers and at around the 0.25μm technology node), CMP has become one of the critical and indispensable pieces of equipment in chip manufacturing. As technology nodes keep shrinking, the number of polishing cycles required for both metals and dielectrics continues to rise, while the demand for uniformity becomes increasingly stringent. Consequently, CMP technology is becoming ever more crucial.

　　Without CMP technology, lithography at higher nodes (below the 0.35μm technology node) would be impossible to implement. At the same time, CMP technology also enables the fabrication of complex multilayer structures. Under 450mm wafer dimensions, the main requirements for CMP technology are:

　　(1) As the feature linewidth of semiconductor devices continues to shrink, the resolution requirements for lithography equipment are becoming increasingly stringent.

　　(2) The need for the development of multi-layer interconnection technology;

　　(3) The need for applying shallow-trench isolation technology;

　　(4) The need to introduce copper processing technology;

　　(5) Requirements for low-K dielectric processes;

　　(6) Requirements for HKMG technology;

　　(7) Requirements for FinFET technology.

　　Therefore, the technical research and exploration of CMP equipment for 450mm wafer sizes hold significant forward-looking practical value.

　　Latest developments in 1CMP consumables

　　While developing the 450mm CMP equipment, we simultaneously initiated the development of CMP consumables and have already achieved numerous breakthroughs.

　　1.1 Research Progress on New Polishing Liquids

　　In the 450mm CMP process, new polishing slurries are primarily focused on applications in HKMG and FinFET CMP processes. Current research findings on these new polishing slurries indicate that their chemical removal effect is more significant than their mechanical removal effect, thereby reducing defects caused by mechanical action. Moreover, the abrasive materials used in these polishing slurries have largely been replaced with cerium oxide instead of traditional silica abrasives. In the 450mm process, the introduction of three-dimensional gate stack structures for transistors and new materials has made transistor manufacturing increasingly complex and raised ever-higher requirements for process control. Consequently, the selectivity of polishing slurries toward these new materials plays a critical role in determining the success or failure of minimizing defects in the planarization process.

　　The RL310, released by Dow Electronic Materials—a subsidiary of Dow Chemical—features non-abrasive particles and self-stopping capabilities. It has been used for more than three years in 90- to 45-nm processes at 300-mm IDM (Integrated Device Manufacturers). Moreover, its next-generation non-abrasive particle solution has been selected by leading IDMs as the process record for the 14-nm node.

　　1.2 Research Progress on New Polishing Pads

　　The technological advancement of polishing pads has been relatively slower compared to that of polishing slurries. Since the beginning of the 21st century, progress in polishing-pad technology has primarily focused on enhancing process capabilities and reducing process defects. In the 450mm process, the required diameter of polishing pads has reached over 1,067 mm (42 inches). Research is now deepening into how polishing-pad dressing patterns and surface topographies affect the quality of planarization. On the other hand, while ensuring high-quality planarization, studies are also examining polishing-pad surface topography to provide support for maximizing the effectiveness of polishing slurries. Dow Electronic Materials, a subsidiary of Dow Chemical in the United States, has launched the IKONICTM CMP polishing-pad series, which delivers top-level performance. This product is designed for CMP applications at 28nm and smaller technology nodes and is currently undergoing testing and evaluation in both laboratory settings and pilot production lines.

　　1.3 Polishing Pad Refiner

　　3M holds the dominant position in the CMP dresser market. Polishing-pad dressers are used to refine the topography of polishing pads, and research on these dressers focuses on factors such as dresser size, diamond particle size, diamond particle density, arrangement pattern, and bonding method. In response to the requirements of 450mm process lines, 450mm CMP dressers are larger than their 300mm counterparts. Among these factors, the bonding method for diamond particles is a key area of study—aiming to ensure both extended dresser life and prevention of diamond particle detachment, which could otherwise lead to scratches on the wafer.

　　2. Outlook and Analysis of Key Technologies

　　The aforementioned consumables were developed independently of CMP equipment and have already achieved practical, real-world applications, thereby creating favorable conditions for 450mm CMP. Meanwhile, CMP equipment itself is currently under development. At present, the two major CMP equipment manufacturers—AMAT (Applied Materials, U.S.) and Ebara (Japan)—dominate over 90% of the 300mm wafer market. As for 450mm wafers, these two equipment manufacturers will undoubtedly be eager not to lag behind; they are quietly investing in R&D of both equipment and processes to seize the initiative and gain a foothold in the market ahead of their competitors.

　　For 450mm CMP equipment, the main trends are:

　　2.1 System Integration Technology

　　The CMP’s primary processes—targeting STI (shallow trench isolation), ILD (interlayer dielectric), tungsten, and copper—are set to continue into the 450mm process. However, starting from the 14nm node, both logic chips and memory chips will inevitably require HKMG (high-K metal gate) and FinFET structures. Therefore, the requirements for HKMG and FinFET processes represent the main driving force behind the development of CMP technology for 450mm wafers.

　　As the film thickness in HKMG and FinFET structures continues to shrink below 10 nm, higher demands are placed on the precision and control capabilities of CMP equipment. Among all process schemes for 300-mm CMP, the three-step process (using three polishing machines) developed by AMAT (Applied Materials) has become the mainstream approach. However, in 450-mm CMP processes, there is a potential shift back to a two-step process. This shift is driven not only by the need to reduce the physical footprint of CMP equipment but, more importantly, by the growing demand for real-time control of film thickness. Consequently, this also places higher requirements on the R&D of key CMP components—various polishing slurries. Fortunately, currently, the development of polishing slurries has been carried out independently of 450-mm CMP equipment and has already yielded tangible results.

　　Since the 450mm CMP process plan may revert to a two-step process, the requirement can only be addressed through the overall layout of the CMP equipment. Therefore, the key challenge in the equipment’s overall layout is that it must not only accommodate the functional requirements of various CMP processes but also reflect the need for a completely redesigned equipment layout—rather than simply being an extension of the existing 300mm wafer CMP equipment layout.

　　2.2 Multi-Region Pressure Control Carrier Technology

　　Since the polishing motion mode of CMP equipment was standardized to rotational motion during the 200mm process and has demonstrated its superiority, in the 450mm process as well, CMP equipment will continue to employ the rotational motion mode for polishing. On the other hand, to address the issue of inconsistent overall removal rates associated with the rotational motion mode during the polishing process, multi-zone pressure-control carrier technology has been developed and will be further implemented in 450mm CMP equipment. However, from a technical standpoint, the following challenges remain:

　　(1) Compared to the multi-zone pressure-controlled carrier used in 300mm CMP equipment, the carrier for 450mm wafer CMP equipment will adopt a design with 6 to 8 zones, resulting in a more complex carrier structure and increased manufacturing complexity of related thin-film components.

　　(2) One of the carrier’s consumables—the retaining ring—needs to be designed with a “quick-change” approach, which increases the complexity of both the retaining ring and the carrier’s structure.

　　(3) Due to the increasingly lower pressure requirements for copper polishing and HKMG process polishing (which may be less than 2.07×10⁻³ MPa), high precision in maintaining both the overall polishing pressure and the regional pressure distribution is essential. Consequently, the control resolution of the fluid system must be better than 0.14×10⁻³ MPa, further enhancing the resolution accuracy of low-pressure fluid control valves. By adopting a fluid system with ultra-low pressure and superior pressure-maintaining accuracy, along with its corresponding control system, we have developed a unique technology for 450mm CMP equipment.

　　2.3 Polishing Pad Dressing Technology

　　Since the emergence and widespread adoption of CMP technology, diamond-wheel dressing has consistently been the standard technique for maintaining a stable removal rate and extending the service life of polishing pads. However, as wafer diameters have increased and new types of polishing pads have been introduced, diamond-wheel dressing technology has increasingly focused on minimizing process defects. Nevertheless, the risk of diamond-wheel debris shedding remains, which poses a critical challenge for 450mm processes. Consequently, the development of a polishing-pad dressing technique and method that generates no contamination has become a unique and essential technology for 450mm CMP processes.

　　2.4 Endpoint Detection Technology

　　Since CMP processes for films such as STI, HKMG, and Copper involve controlling film thicknesses below 10 nm, endpoint detection accuracy is a key technological challenge that needs to be addressed.

　　(1) The full-section eddy current scanning technology will be extended to an application range of 450 mm. However, the eddy current frequency will be increased, and the real-time scanning algorithm will be refined in response to the diversification of testing environments, thereby establishing a unique technology tailored specifically for the 450-mm CMP process.

　　(2) The full-section optical scanning technology will also be extended to 450mm applications, and white-light sources will continue to be used. However, the light source will need to be determined through experimentation. Research on real-time scanning algorithms will evolve alongside the diversification of testing environments and polishing material types, and these algorithms will be refined through experiments to establish a set of technologies unique to the 450mm CMP process.

　　2.5 Post-Cleaning Technology

　　In the 200mm process, the post-CMP cleaning system can be used in conjunction with CMP offline. As we move to the 300mm process, the integrated post-CMP cleaning system has become a standard module for CMP equipment.

　　In integrated circuit manufacturing, the cleaning process accounts for approximately 30% of the entire fabrication workflow. As device feature sizes continue to shrink, not only are increasingly stringent requirements placed on cleaning effectiveness, but also ever more rigorous demands are imposed on minimizing damage to the device’s microstructure. At the 14nm node, the post-CMP cleaning specifications mandate that defects larger than 30nm should be fewer than 10 particles—a challenge that poses even greater difficulties for post-CMP cleaning processes.

　　In 300mm CMP equipment technology, due to both technical requirements and commercial supply-chain considerations, Applied Materials has developed a fourth-generation post-cleaning system. The vertical cleaning and IPA-drying post-cleaning technology, exemplified by the Reflexion LKCMP equipment, has been widely adopted since 2008 and has since been extended to the 14nm process node. However, even though the Reflexion LKCMP employs the most advanced post-cleaning technology available today, challenges still remain at the 14nm process node.

　　In the 450mm cleaning technology, supercritical cleaning technology has been developed and is now undergoing testing and evaluation. Given its advantages—such as ultra-clean and environmentally friendly performance, water resource savings, and minimal damage to device microstructures—supercritical cleaning technology could be widely adopted in post-CMP cleaning processes. However, due to the comprehensive integration requirements with CMP equipment, whether the 300mm post-CMP cleaning technology can be directly extended to 450mm or whether a revolutionary new approach must be pursued remains inconclusive at present.

　　Therefore, in the 450mm process, a brand-new post-CMP cleaning technology is an inevitable requirement, giving rise to its unique characteristics.

　　3 Conclusion

　　This article provides a comprehensive analysis of the historical development of integrated circuits. Building on this analysis and in conjunction with trends in consumables, it lays the foundation for the development of 450mm CMP equipment. Furthermore, it outlines and analyzes five key technologies for 450mm wafer CMP.

　　In 2013, major semiconductor manufacturers did not significantly cut their capital expenditures as analysts had anticipated. On the contrary, the “big three”—Intel, TSMC, and Samsung—continued to expand their production capacity for advanced processes and all aimed to outperform their rivals in processes below 20nm and in 450mm wafer technology. Over the next few years, these three companies will undoubtedly keep investing, thereby accelerating the demand for research and industrialization of CMP equipment. (Reprinted from: Microelectronics Manufacturing)