CMP Industry Technology Development Trends

In recent years, with the rapid advancement of CMP industry technology, the future application prospects and existing challenges of advanced CMP technologies have become a hot topic of great concern. Currently, the main CMP technologies for nodes below 10nm include: FinFET STICMP, FinFET PolyCMP, FinFET RMGWCMP, CuCMP, and TSVCuCMP. On the path toward mastering CMP technologies below 10nm, several key challenges remain: reducing defects and achieving uniformity control in FEOLCMP; precisely controlling the height of metal gates in MOLCMP; reducing defects and ensuring self-aligned contacts.

In recent years, as... CMP The rapid advancement of industrial technology, The future application prospects and existing challenges of advanced CMP technology are hot topics of great concern. Currently, For 10nm The following CMP The main technologies are: FinFET STI CMP ， FinFET Poly CMP ， FinFET RMG W CMP ， With CMP ， TSV Copper CMP Wait. And while conquering 10nm The following CMP On the path of technology, the challenges ahead are: FEOL CMP Reduction of defects and control of uniformity in the medium, MOL CMP height control of the metal gate, defect reduction, self-aligned contacts, and BEOL CMP Optimization of ruthenium polishing, cobalt metallization, defect reduction, and process control. CMP We must break through technological bottlenecks to achieve sustained development and application in advanced technologies. All parties should actively collaborate and jointly address these challenges.

Issues and challenges currently亟待 addressed include CMP consumables technology, CMP technology for advanced nodes, CMP hardware equipment and control systems, as well as new CMP applications and simulation technologies. From March 15 to 16, 2015, at the CMP and Post-CMP Cleaning Session of the China International Semiconductor Technology Conference, numerous experts and scholars delivered insightful presentations.

I. CMP Consumables Technology

CMP consumables technology primarily refers to the analysis of how polishing pads, polishing slurries, and dresser tools—among other CMP-related materials—affect the outcome of the CMP process. At present, the evaluation of CMP mainly focuses on aspects such as the degree of planarization, technical reliability, and defect-control capability. Among these, defect control—including the analysis of impacts from scratches, particles, and corrosion—is a key area of research. KeeJoon Oh from Hynix, Mr. Hongtao Liu from SMIC, HJ Yang from Entegris, and Alex Wang from Cabot each conducted studies from the perspective of polishing slurries, analyzing their impact on defect control during the CMP process. Haiyu Kui from SYMicro-Electronic Tech. Ltd also carried out related research from the perspectives of dresser tools and polishing pads.

Mr. Liu Hongtao summarized the challenges faced in 32/28nm BEOL Cu CMP, with particular emphasis on how to reduce scratches and particles. The report pointed out that it is crucial to ensure the quality of consumables, especially in the selection and formulation of polishing slurries. It is necessary to carefully adjust the chemical composition of the slurry and choose an appropriate polishing agent. On this basis, further adjustments can be made to the corresponding CMP process parameters, including optimizing the timing balance between the polishing and cleaning stages.

Kee Joon Oh presented the development history of polishing liquids, which has been driven by the goal of reducing scratches and defects and achieving planarization. The evolution of abrasives used in these liquids has progressed from calcined silica to silica gel, and then from calcined cerium dioxide to non-calcined cerium dioxide. Subsequently, Kee introduced a non-calcined cerium-dioxide polishing liquid designed for STICMP, and presented experimental results from various perspectives, including scratch defects, removal rate and stability, mixing ratio, selectivity, service life, and cycle performance. In conclusion, while this polishing liquid exhibits several advantages, further improvements in performance are still needed, underscoring the importance of collaborative research between industry and academia.

Under the growing trend of increasingly stringent control over scratch and polishing slurry particle size, H.J. Yang proposed an idea: to remove large particles that fail to meet the required specifications from the polishing slurry by means of filtration. In his report, he provided a detailed description of the filtration model and the mechanism behind clogging, along with corresponding solutions—POT and POD filtration. Finally, Mr. Yang introduced nanofiber filtration technology, which addresses the need for filtering even smaller-sized particles. The key to this technology lies in reducing both the initial pressure and the rate at which pressure increases, thereby extending the service life and enhancing both particle removal efficiency and particle-capturing capacity.

Alex Wang introduced Cabot’s newly developed silicone polishing slurry—D9228—for oxide layer polishing. This slurry boasts advantages such as high dilution ratio, stability, low defect levels, and cost-effectiveness. Moreover, D9228 employs a charge-attraction mechanism to enhance its removal efficiency. Mr. Wang also presented polishing data for D9228 on 300mm wafers, including metrics such as defect levels, removal rates, and removal stability. A comparative analysis with similar polishing slurries clearly demonstrated D9228’s superior performance in terms of improved efficiency and reduced component content. This also indirectly highlighted the critical role that the selection of polishing slurry plays in determining the quality of CMP results.

Haiyu Kui used software to build and simulate models from the perspectives of dressing tools and polishing pads, in order to calculate the relationship between the penetration depth of diamond particles from the dressing tool into the polishing pad and their motion trajectories. On this basis, he varied the mathematical relationship between these two factors to analyze their impact on polishing performance.

II. CMP Technology Under Advanced Nodes

As the semiconductor industry continues to advance and feature sizes become increasingly smaller, CMP—a crucial component of the manufacturing process—has also come under growing demand for advancements in CMP technologies tailored to advanced nodes. With shrinking feature sizes, existing technologies are facing significant bottlenecks, such as ever-tighter requirements for defect control. In response to this trend, three scholars—Yehwan Kim from Samsung, Yung-Tai Hung from Macronix, and Chen Wang from Anji Microelectronics—shared their insights on “Methods for Controlling Defects in CMP Processes at Ultra-Small Feature Sizes.”

Yehwan Kim provided a brief explanation of contact modes and potential types of scratches at the 10nm feature size. When discussing measures to reduce scratches, Yehwan Kim analyzed that, compared to larger feature sizes, it is necessary to control particle diameter, ensure the dispersion stability of the polishing slurry, and precisely control particle shape. The report then introduced cerium dioxide abrasives, which possess electrokinetic properties and exhibit adsorption capabilities toward PMMA, while also featuring a relatively small particle diameter. In addition, Yehwan examined the technical challenges currently faced at extremely small feature sizes: While controlling particle diameter reduces abrasive particle size, thereby minimizing scratches, this also leads to a decrease in removal rate and an increase in polishing time. Striking the right balance between these two parameters to achieve optimal performance is now the primary focus of ongoing research. Finally, Yehwan showcased Samsung’s cerium dioxide abrasive polishing slurry—NSC polishing slurry—for use below the 10nm feature size, and compared it with other polishing slurries, highlighting its excellent polishing performance characterized by high removal rates, nanoscale abrasive particle size, and low defect levels.

Yung-Tai Hung primarily analyzed the defect of abnormal color changes occurring on polished surfaces and proposed corresponding solutions. Regarding these color anomalies, he pointed out that two potential defects might be responsible: first, residual copper or barrier layer material; second, local variations in coating thickness. For the first issue, Yung-Tai Hung initially hypothesized that the root cause might be residual copper or chemical substances left behind after polishing. However, subsequent experiments revealed no copper residue on the copper layer itself after polishing. Despite this, the polished surfaces still exhibited color abnormalities, indicating that copper residue was not the underlying cause. After conducting additional experiments—such as tests specifically targeting copper polishing, barrier-layer polishing, and consumable materials—he adjusted several factors, including the flow rate of the copper-polishing solution, the speed and duration of deionized water rinsing after copper polishing, the distribution pattern of the copper-polishing solution, and the selection ratio of polishing solutions. Eventually, he elucidated the mechanism behind the local thickness variations: during copper polishing, the presence of a corrosion inhibitor led to uneven dishing distribution on the surface after polishing. Moreover, this inhibitor also affected the surface morphology during barrier-layer polishing, ultimately resulting in non-uniform thickness and color abnormalities. In summary, while the copper corrosion inhibitor effectively protects the copper surface, its residual traces and uneven distribution can interfere with subsequent barrier-layer polishing, causing thickness inconsistencies and, consequently, color anomalies. Finally, Yung-Tai Hung proposed appropriate improvement measures: more effective removal of corrosion-inhibitor residues after polishing, or the use of copper-polishing solutions with lower corrosion-inhibitor content.

Chen Wang took the recent barrier layer polishing process as a starting point to introduce various polishing requirements, including flatness, low defect density, wide process window, and low cost. He also highlighted the challenges faced after polishing, such as non-uniformity in post-polishing surface topography, the formation of sharp edges (fangs), corrosion, scratches, and residual particles. In the remainder of his presentation, Mr. Wang elaborated on specific solutions for each of these defect issues: 1. Regarding non-uniform post-polishing surface topography, the report pointed out that the key lies in the selectivity of the removal rates during the polishing process. If the copper removal rate exceeds that of the dielectric layer, dishing and erosion will become increasingly severe as polishing progresses. Conversely, if the copper removal rate is lower than that of the dielectric layer, protrusions or more severe erosion may occur. However, when the copper removal rate equals that of the dielectric layer, theoretically the final surface topography will be largely independent of the overall dielectric loss. Initially, erosion will be significant but will gradually decrease and stabilize at a low level. 2. For achieving a wide process window, the ideal scenario is for the removal rates to follow this sequence: barrier layer > oxide layer > dielectric layer = copper layer. The barrier layer polishing solution produced by Anji comes very close to this target. Moreover, since the copper removal rate is nearly equal to that of the dielectric layer, the final surface topography becomes largely insensitive to dielectric loss. As a result, the over-polishing time window is significantly widened, and both the allowable concentration ratios and hydrogen peroxide windows are considerably larger. 3. Concerning the issue of sharp edges (fangs), the report provided a detailed explanation of their underlying mechanism: local oxide removal occurs too rapidly, leading to steps and height differences on the surface after polishing. To reduce these steps, the oxide removal rate must exceed that of copper. On the other hand, to prevent fangs from forming altogether, the local oxide removal rate needs to match the copper removal rate. By optimizing the formulation of Anji’s barrier layer polishing solution, it is possible to reduce dishing from 500 Å to 170 Å and fangs from 200 Å to below 20 Å.

III. CMP Hardware Equipment and Control

As research into CMP technology continues to deepen, researchers have found that, in addition to placing higher demands on the performance of consumables, improving post-CMP results also requires increasingly sophisticated CMP hardware equipment and control systems. Jun Yang from SMIC, Ding Yi from HuaLi Microelectronics in Shanghai, H. X. Zhang from Applied Materials, and Xu Ning from Xi'an Jiaotong University each presented their perspectives on CMP hardware equipment, control systems, and corresponding testing methods.

JunYang provided a brief introduction to the concept of “Advanced Process Control (APC)” and seamlessly integrated it with the current challenges facing CMP technology—such as improved uniformity, tighter post-etch thickness control, reduced wafer-to-wafer thickness variation, and precise edge profile adjustment. He proposed strategies for controlling post-CMP surface morphology at different stages, managing edge profiles, and adjusting the timing of the polishing tools. Finally, he emphasized that the future development of CMP is inseparable from the support of advanced process control, and how to more effectively integrate these two approaches will be the key focus of future research.

DingYi emphasized that, as an integral part of the process control, measuring copper thickness during CMP is of paramount importance. He introduced two commonly used systems for measuring copper thickness. The Rudolph Metalpulse system employs photoacoustic technology for measurement, while the Kla-Tencor Aleris system measures copper thickness by collecting information from two types of light and analyzing their polarization and spectral characteristics. Following his presentation, both testing systems were demonstrated and compared. The results showed that the Rudolph Metalpulse method yielded measurements with larger amplitude and poorer uniformity for bondpads, whereas its measurements for OCD pads exhibited better uniformity and greater stability. On the other hand, the Kla-Tencor Aleris system had distinct advantages in measuring dielectric layers, as it could accurately reflect the overall topography of the entire wafer and demonstrated excellent convergence and stability. Finally, he pointed out that different testing methods should be employed to monitor and control CMP processes tailored to specific materials and process stages.

H. X. Zhang introduced a real-time endpoint detection system called Fullvision, which can detect the endpoint for a variety of materials—including ILD oxide, STI oxide, poly, Cu, and W—thus significantly boosting production on actual production lines. Compared with traditional detection systems such as APC and iAPC, Fullvision offers substantial advantages. However, at the end of his presentation, Mr. Zhang also pointed out that Fullvision currently has some areas needing improvement—for instance, since the endpoint detection signal is derived from the dielectric layer, the endpoint timing is affected by the thickness of the CVD-deposited film.

Xu Ning conducted nano-scratching experiments on cerium dioxide tips on copper surfaces, revealing the mechanisms behind scratch formation involving adhesion, plowing, and shearing. By combining the experimental data obtained from such studies with appropriate process monitoring techniques, it is possible to achieve precise control over scratch formation during CMP processes.

IV. New CMP Applications and CMP Modeling & Simulation

As feature sizes continue to shrink, it is inevitable that new definitions will emerge for future CMP processes. To study such CMP processes, researchers will increasingly rely on modeling and simulation techniques. Professor Lu Xinchun from Tsinghua University first introduced the Universal-300 polishing machine produced by Tianjin HuaHai Qingke Mechatronics Technology Co., Ltd. He then proposed a research approach that leverages simulation to enhance polishing performance. Following this, he presented his findings from three perspectives: mechanical simulation of CMP at the wafer scale, molecular dynamics simulation at the atomic scale, and experimental studies on material removal at the atomic scale. The simulation of CMP processes is extremely complex and involves numerous factors, including the polishing head, polishing pad, and polishing slurry. At the wafer scale, key parameters to analyze include downward pressure, kinetic parameters, polishing slurry characteristics, and polishing pad properties. The simulation results obtained encompass variables such as temperature, sliding distance, polishing slurry distribution, and pressure distribution. These results were presented from two angles: kinematic simulation and contact stress analysis, both of which contribute to understanding the mechanics of CMP. At the atomic scale, Professor Lu conducted molecular dynamics simulations from two perspectives—mechanical action and mechanochemical action—and illustrated the mechanisms underlying the CMP process with abundant visual materials, diagrams, and animations. Finally, in the experimental study on material removal at the atomic scale, he used AFM and TEM to investigate how factors such as applied load, sliding speed, scanning range, and humidity influence the depth of material removal. In conclusion, combining simulation results with experimental data, Professor Lu elucidated the material removal mechanism in CMP processes, confirming that atomic-layer material removal is primarily driven by tribochemical effects.

CMP Technological development is advancing rapidly and becoming increasingly complex, while challenges are mounting. As feature sizes reach... 10nm When below this level, the selection of materials with high removal rates becomes crucial. dishing/erosion Control and ensuring uniformity have become even more challenging. Currently, the challenges we face include: 10nm And below CMP Technology, FinFET of the CMP ，450mm Wafer's CMP ...the exploration and search for new flattening methods, and so on, while... CMP It itself also needs to evolve toward automation, refinement, and generalization.

The speakers who participated in this CMP and post-CMP cleaning report include: Yongsik Moon from Global Foundries, Kee Joon Oh from SK Hynix, Liu Hongtao from SMIC, HJ Yang from Entegris, Alex Wang from Cabot, Haiyu Kui from SYMicro-Electronic Tech., Ltd., Yehwan Kim from Samsung, Yung-Tai Hung from Macronix, Chen Wang from AMLink Microelectronics, Jun Yang from SMIC, Ding Yi from Shanghai Huali Microelectronics, Xu Ning from Xi'an Jiaotong University, H. X. Zhang from Applied Materials, Viorel Balan from CEA-LETI, Yoshitaka Tsunashima from Nitta-Hass, Feng Yulin from Tianjin University of Technology, Zhang Qi from North Carolina Agricultural & Technical State University, Lu Xinchun from Tsinghua University, Chen Zhaozhang from National Taiwan University of Science and Technology, and Lixiao Wu from Lanzhou University of Technology. The moderators are: K. C. Wu and David Huang from Cabot, Wang Yuchun from AMLink Microelectronics, Kent Liu, and Zhang Kailiang from Tianjin University of Technology.

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