Local strain technology is expected to enhance FDSOI performance.

The French research institute CEA-Leti has announced the development of two new technologies that can induce localized strain in fully depleted silicon-on-insulator (FDSOI) silicon channels, a process that holds promise for enabling next-generation FDSOI circuits with faster speeds, lower power consumption, and higher performance. STMicroelectronics (ST) and GlobalFoundries are advocating the adoption of FDSOI in advanced chips, viewing it as a viable approach to achieving world-class energy efficiency without the complexity and high costs associated with FinFET processes. Strain in the crystal lattice is typically achieved by...

The French research institute CEA-Leti announced the development of a fully depleted silicon-on-insulator (SOI) device. FDSOI ) Silicon channel process-induced local strain 2 The new technology holds promise for enabling the next generation of devices that are faster, lower-power, and higher-performance. FDSOI Circuit.

　 STMicroelectronics (STMicroelectronics; ST) and GlobalFoundries Initiative for adoption in advanced chips FDSOI and regard it as a method capable of achieving world-class energy efficiency, without having to face challenges such as... FinFET The complexity and high cost of the manufacturing process.

　　Strain on the crystal lattice is commonly used to enhance conventional planar structures. CMOS With FinFET CMOS Its actionability. Nowadays, Leti Then it is proposed to use it in the next generation. FDSOI On the circuit, to achieve the same benefits. ; This enables higher performance at the same power consumption.

　　Whether it is FinFET or FDSOI The manufacturing process is extremely important because... FDSOI in the p- Channel FET Need silicon-germanium (SiGe) The compressive strain in the channel material also requires tensile strain to improve silicon crystals. n- Channel FET 。 Leti Two new technologies have been developed for two different manufacturing processes, enabling them to... MOSFET Induce up to 1.6GPa Local strain.

　　 LETI indicates that, due to 28nm FDSOI Strain is not necessarily required; these two technologies primarily target... 22/20nm Node. The first technology utilizes from SOI Loose on top of the film SiGe Transfer strain. This can be used to enhance the short-channel electromigration rate. 20% The above.

　　The second technological approach relies on the creep of buried oxide layers under high-temperature annealing, resulting in tensile strain that is introduced into the overlying epitaxial layer. Leti It is pointed out that this latent transformation can also be used to introduce compressive strain.

　　This strain channel can increase. CMOS The transistor’s on-state current, as well as achieving higher performance at the same power level, or reducing power consumption at a given performance level.

Key words: