Employing a gap-inhibition-type tungsten-filled contact region process to reduce yield loss.

Author: Jonathan Bakke, Global Manager of Contact and Interconnect Product Lines, Metal Deposition Products Division, Applied Materials. In earlier technology nodes, when device dimensions were larger, tungsten (W) filling could be achieved using nucleation and planarization chemical vapor deposition (CVD) techniques. Today, however, due to the extremely small openings in vias, dangling structures are prone to occur. As a result, the conformal growth stage—during which the thin film is supposed to grow uniformly across the surface—may close or become pinched off before filling is complete, leaving behind voids. Even if no voids are present, since the fill material grows from the sidewalls, a central gap will inevitably form during conformal deposition. These characteristics make it...

Author: Jonathan Bakke, Global Manager, Contact and Interconnect Product Lines, Metal Deposition Products Division, Applied Materials

In earlier technology nodes, due to the larger device dimensions, nucleation- and planarization-based chemical vapor deposition (CVD) techniques could be used for tungsten (W) filling. Today, however, because the ultra-small openings at the vias are prone to dangling structures, the conformal growth stage—during which the thin film grows uniformly across the surface—may close or become interrupted before filling is complete, leaving behind voids. Even if no voids are present, since the fill material grows from the sidewalls, a central gap will inevitably form during conformal deposition.

　　These properties make the ultra-thin nucleation layer highly susceptible to penetration during chemical-mechanical polishing (CMP), allowing CMP slurry to enter and thereby damaging the tungsten plugs. This can lead to high electrical resistance or even complete failure of the interconnects responsible for transmitting transistor signals. In advanced chip designs, with their high-density features and limited availability of extra vias, a single small defect—such as an unanticipated hole—can cause total device failure, resulting in severe yield losses (Figure 1).

Figure 1: In the figure above, the y-axis shows the yield loss of the device, while the x-axis represents the via defect rate. A defect rate of just one in a billion can lead to a yield loss of more than 15% for chips manufactured at the 20nm node, and in... 。 This situation will be even more severe in devices with smaller nodes.

　　 Our new approach employs a unique “selective” inhibition mechanism that enables bottom-up filling without causing gaps or voids. A special pre-treatment of the upper region of the nucleation layer promotes tungsten growth from the bottom up, thereby minimizing the formation of voids or contact-area gaps caused by pinching.

This “gap-inhibition-type tungsten” The “filling process” (SSW) effectively optimizes the volume of tungsten, creating a more robust nucleation surface that facilitates subsequent integration processes. This approach also reduces the requirements for CMP and dielectric etching processes, leading to improvements in performance, product design, and yield.

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